基于XilinxIP核的任意信号发生器的设计
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周欢(1993—),女,硕士研究生,研究方向为电能质量检测。

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TP274

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Design of Arbitrary Signal Generator Based on Xilinx IP Core
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    摘要:

    基于 Xilinx IP 核设计一个任意信号发生器,可以生成任意频率、幅值和相位的正余弦、三角波、方波、锯齿波等信号,在工程设计中可以方便的用于仿真模拟设计。 首先对 DDS IP 核进行配置设计,添加乘法器 IP 核产生不同幅值的正余弦波形,添加多个 DDS IP 核设置不同的频率控制字和相位宽度以及初始相位产生不同频率和相位的正余弦信号,但是 DDS IP 核只能通过正余弦信号采样查找表生成正余弦信号,可以添加 ROM IP 核导入不同信号的数据,通过改变频率控制字控制寻址地址以及设置 ROM 地址的初始值从而实现任意信号幅值、频率、相位的信号发生器的设计。仿真结果显示可以输出不同频率、相位的正余弦波、三角波、方波、锯齿波等信号。 该方法整体设计方案可行,易于调整,可以达到预期结果,在工程上有一定的应用价值。

    Abstract:

    In this paper, an arbitrary signal generator was designed based on Xilinx IP core. Sine wave, triangle wave, square wave, sawtooth wave and other signals can be generated at any frequency, amplitude and phase. It can be conveniently used in simulation design in engineering design. First of all, through the DDS IP core con- figuration design, it has different amplitude sine wave by adding multiplier IP core, and different frequency and phase sine wave by adding multiple DDS IP core to set the cosine signal frequency and phase control word width and initial phase. However, the DDS IP core can only generate sine and cosine signals by means of the sine and cosine sampling look-up table. Then the data can be imported through the adding of ROM IP. By changing the frequency control word, addressing address and setting the initial value of the ROM address, the signal generator of arbitrary signal amplitude, frequency and phase can be realized. The simulation results show that different frequency and phase of sine wave, triangle wave, square wave, sawtooth wave and other signals can be output. The overall design scheme of this method is feasible, and it is easy to adjust the design of parameters, which can achieve the desired results, and has certain application value in engineering.

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周欢,陈剑云,钟汉华.基于XilinxIP核的任意信号发生器的设计[J].华东交通大学学报,2018,35(4):112-116.

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  • 在线发布日期: 2021-05-26
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